The embodiments of the invention relate generally to the fabrication of semiconductor devices and more particularly to the fabrication of self-aligned contacts to raised sources and drains of a CMOS structure.
In devices with raised source and drains the source and drain layers are formed above the channel material to achieve low series resistance.
Leading edge CMOS industry is facing strong limitations in lithographic scaling for 10 nm node and beyond. The formation of contacts at advanced nodes is challenging in view of high process complexity and high costs. High-k gate dielectrics are used to scale down the thickness of the gate dielectric.